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| MC74HC574A Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS The MC74HC574A is identical in pinout to the LS574. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip-flops, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be stored even when the outputs are not enabled. The HC574A is identical in function to the HC374A but has the flip-flop inputs on the opposite side of the package from the outputs to facilitate PC board layout. http://onsemi.com MARKING DIAGRAMS 20 PDIP-20 N SUFFIX CASE 738 1 MC74HC574AN AWLYYWW 1 20 20 * * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 266 FETs or 66.5 Equivalent Gates 20 1 SOIC WIDE-20 DW SUFFIX CASE 751D 1 A WL YY WW HC574A AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC74HC574AN MC74HC574ADW MC74HC574ADWR2 Package PDIP-20 SOIC-WIDE SOIC-WIDE Shipping 1440 / Box 38 / Rail 1000 / Reel (c) Semiconductor Components Industries, LLC, 2000 1 March, 2000 - Rev. 8 Publication Order Number: MC74HC574A/D MC74HC574A LOGIC DIAGRAM D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK OUTPUT ENABLE 2 3 4 5 6 7 8 9 11 1 PIN 20 = VCC PIN 10 = GND 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NON- INVERTING OUTPUTS PIN ASSIGNMENT OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK FUNCTION TABLE Inputs OE L L L H Clock D H L X X Output Q H L No Change Z L,H, X X = Don't Care Z = High Impedance II I IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II I IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II I II II I IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII II II I IIIIIIIIIIIIIII II IIIIIIIIIIIIIII IIIIIIIIIIIIIII II IIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIII Design Criteria Value 66.5 1.5 5.0 Units ea ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product W pJ 0.0075 *Equivalent to a two-input NAND gate. http://onsemi.com 2 MC74HC574A II II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIII I II I I I II I I III I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I II II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIII III I II I I IIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII II I I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I III II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature Plastic DIP SOIC Package mW Tstg TL - 65 to + 150 260 _C _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC - 55 0 0 0 + 125 1000 500 400 _C ns tr, tf VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VIH Parameter Test Conditions VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 6.0 - 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 v 85_C v 125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 Unit V Minimum High-Level Input Voltage Vout = VCC - 0.1 V |Iout| 20 A v v v VIL Maximum Low-Level Input Voltage Vout = 0.1 V |Iout| 20 A V VOH Minimum High-Level Output Voltage Vin = VIH |Iout| 20 A Vin = VIH V |Iout| |Iout| |Iout| v 2.4 mA v 6.0 mA v 7.8 mA v 2.4 mA v 6.0 mA v 7.8 mA 2.48 3.98 5.48 0.1 0.1 0.1 2.34 3.84 5.34 0.1 0.1 0.1 VOL Maximum Low-Level Output Voltage Vin = VIL |Iout| 20 A v V Vin = VIL |Iout| |Iout| |Iout| 0.26 0.26 0.26 0.33 0.33 0.33 Iin Maximum Input Leakage Current Vin = VCC or GND 0.1 1.0IIII A 1.0 http://onsemi.com 3 MC74HC574A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I II IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I I I IIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I III I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I Guaranteed Limit Symbol IOZ Parameter Test Conditions VCC V 6.0 - 55 to 25_C 0.5 v 85_C v 125_C 5.0 10 40 160 Unit A Maximum Three-State Leakage Current Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 A ICC Maximum Quiescent Supply Current (per Package) 6.0 4.0 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol IOZ Parameter Test Conditions VCC V 6.0 - 55 to 25_C 0.5 v 85_C v 125_C 5.0 10 40 160 Unit A Maximum Three-State Leakage Current Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND |Iout| = 0 A ICC Maximum Quiescent Supply Current (per Package) 6.0 4.0 A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol fmax Parameter VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 60 2.0 3.0 4.5 6.0 - 55 to 25_C 6.0 15 30 35 v 85_C v 125_C 4.8 10 24 28 4.0 8.0 20 24 Unit Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures 1 and 4) 160 105 32 27 150 100 30 26 140 90 28 24 60 27 12 10 10 15 200 145 40 34 190 125 38 33 175 120 35 30 75 32 15 13 10 15 240 190 48 41 225 150 45 38 210 140 42 36 90 36 18 15 10 15 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) ns tTLH, tTHL Maximum Output Transition Time, any Output (Figures 1 and 4) ns Cin Maximum Input Capacitance pF pF Cout Maximum Three-State Output Capacitance, Output in High-Impedance State NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 24 CPD Power Dissipation Capacitance (Per Enabled Output)* pF * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 4 II I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I I I I I I I IIIIIIIIIIIIII I I IIII III IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol tr, tf tsu tw th Maximum Input Rise and Fall Times Minimum Pulse Width, Clock Minimum Hold Time, Clock to Data Minimum Setup Time, Data to Clock Parameter http://onsemi.com MC74HC574A Fig. 1 1 3 3 5 VCC Volts 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.6 6.0 - 55 to 25_C Min 5.0 5.0 5.0 5.0 50 40 10 9.0 75 60 15 13 1000 800 500 400 Max Guaranteed Limit Min 5.0 5.0 5.0 5.0 95 80 19 16 65 50 13 11 v 85_C 1000 800 500 400 Max Min 110 90 22 19 5.0 5.0 5.0 5.0 75 60 15 13 v 125_C 1000 800 500 400 Max Unit ns ns ns ns MC74HC574A SWITCHING WAVEFORMS tr CLOCK 90% 50% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL tPHL Q tf VCC 1.3 V GND tPZL 1.3 V tPZH Q tPHZ 10% 90% tPLZ GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE 3.0 V Figure 1. Figure 2. VALID VCC DATA 50% GND tsu CLOCK th VCC 50% GND D1 3 D0 2 EXPANDED LOGIC DIAGRAM C Q D C Q D C Q D C Q D C Q D C Q D C Q D C Q D 11 1 19 Q0 18 Q1 Figure 3. D2 TEST POINT D3 OUTPUT DEVICE UNDER TEST D4 4 17 Q2 5 16 Q3 6 15 Q4 CL* D5 *Includes all probe and jig capacitance 7 14 Q5 Figure 4. D6 8 13 Q6 TEST POINT OUTPUT DEVICE UNDER TEST 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. D7 9 12 Q7 CLOCK OUTPUT ENABLE CL* *Includes all probe and jig capacitance Figure 5. Test Circuit http://onsemi.com 6 MC74HC574A PACKAGE DIMENSIONS PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E 11 -A- 20 B 1 10 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 -T- SEATING PLANE K M E G F D 20 PL N J 0.25 (0.010) M 20 PL 0.25 (0.010) TA M M TB M DIM A B C D E F G J K L M N SO-20 DW SUFFIX CASE 751D-05 ISSUE F D A 11 X 45 _ q NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ H M B M 20 10X 0.25 E 1 10 h 20X B 0.25 M B TA S B S A SEATING PLANE DIM A A1 B C D E e H h L L 18X e A1 q T C http://onsemi.com 7 MC74HC574A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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